A bus system is a chip-to-chip electronic communications system in which one or more slave devices are connected to, and communicate with, a master device through shared bus signal lines. FIG. 1 illustrates in block diagram form a bus system. The bus system includes a Master control device (M) that communicates with one or more Slave devices (D) via a bi-directional data bus. Typically, the bidirectional data bus comprises a plurality of bus signal lines, but for simplicity, FIG. 1 illustrates only one bus signal line. The terms bus signal line and channel are used synonymously herein. Thus, it will be understood that the data bus includes many channels, one for each bit of data. Each bus signal line terminates on one side at an I/O pin of the master device and terminates on its other side at one end of a resistive terminator (T). The resistance of the terminator is closely matched to the loaded impedance, Z.sub.L, of the bus signal line to minimize reflections and absorb signals sent down the bus signal line toward the terminator. The opposite end of the terminator is connected to a voltage supply that provides an AC ground and sets the DC termination voltage of the bus signal line. The positions along the bus signal line tapped by the Master terminator, and Slaves are labeled P.sub.M, P.sub.T, and P.sub.1 -P.sub.N, respectively.
Bus systems are typically designed to work with several configurations to allow system flexibility. For example, the bus may have several connector slots for inserting individual Slaves or Modules of Slaves, and each Module may have different numbers of devices. This allows the user to change the number of chips that operate in the bus system, allowing small, medium, and large systems to be configured without complex engineering changes, such as changes to the printed circuit board layout. FIG. 2 illustrates a Bus System that provides this flexibility by providing three connectors for three Slave Modules. This figure does not necessarily illustrate the physical layout of an actual system, but shows the electrical connections of the Bus System. The first Module is shown with eight Slaves, the second with four Slaves, and the third Modules with no Slaves. The third Module serves only to electrically connect the terminator to the bus signal line. For simplicity, this configuration can be referred to as an 8-4-0 configuration, and many other configurations are possible by inserting different Modules into the three connector slots (e.g. 8-8-8, 4-0-0, etc.). As in FIG. 1, FIG. 2 designates the points at which each device taps the bus signal line (e.g. Slave B.sub.2 taps the bus signal line at point P.sub.B2). The Bus System of FIG. 2 is very flexible; however, this flexibility results in configuration-dependent and position-dependent channel characteristics that lead to signaling complexities and reduce the reliability of data transmission through the system.
FIG. 3 diagrams structure and electrical properties of a bus signal line in a populated Module of the Bus System of FIG. 2. The portion of the bus signal line that connects to the Slaves forms a repetitive structure of signal line segments and Slaves that can be modeled as a transmission line of length d, with electrical characteristics as shown. In FIG. 3 L.sub.o is the inductance per unit length, C.sub.o is the capacitance per unit length, G.sub.p is the dielectric conductance per unit length, and R.sub.s is the conductor resistance per unit length. The lossy, complex characteristic impedance of such transmission line is given by: ##EQU1##
However, assuming R.sub.s and G.sub.p are small, the characteristic impedance of the bus signal line segment is closely approximated by the simpler equation Zo=Lo/Co.
FIG. 3 also shows the dominant electrical properties of the Slaves I/O pins where L.sub.I is the effective input inductance, C.sub.I is the effective input capacitance, and R.sub.I is the effective input resistance. This input resistance incorporates all input losses including metallic, ohmic, and on-chip substrate losses; is frequency dependent; and tends to increase with frequency. However, assuming that the input capacitance dominates the input electrical characteristics of the Slave (i.e. Xc=1/(2.PI.fC.sub.I)&gt;&gt;X.sub.L =2.PI.fL.sub.I and Xc=1/(2.PI.fC.sub.I)&gt;&gt;R.sub.I) at the system operating frequency, the effective loaded impedance of the bus signal lines is closely approximated by: ##EQU2##
This equation implies that the lumped capacitance of the Slaves' I/O pins is distributed into the effective impedance of the transmission lines. However, the repetitive arrangement of Slaves at intervals of length d along the bus signal line causes the bus signal line to possess a multi-pole low-pass filter characteristic. This lowpass characteristic essentially limits the maximum data transfer rate of the bus system. The cut-off frequency of the channel increases as the number of devices on the channel decreases; as the device spacing, d, decreases; and as the input capacitance, C.sub.I, decreases. FIGS. 4, 5 and 6, illustrate these effects. Additionally, dissipative sources of loss such as the dielectric of the bus' printed circuit board substrate, the skin effect resistance of the bus' metal traces, and the slave devices' input resistances, R.sub.I, also contribute to the low-pass characteristic of the bus signal line, further reducing the usable bandwidth. FIG. 7 illustrates this. For any number of Slaves, it is clearly desirable to have minimum device pitch, d; minimum input capacitance, C.sub.I ; and minimum loss (e.g. R.sub.I) for maximum frequency operation of the system.
For these reasons, the device pitch, d, is generally kept at a fixed, minimum practical length which is determined by space limitations and printed circuit board technology. Likewise input capacitance is kept to a fairly tight, minimum range determined by silicon ESD requirements and processing limitations. Losses are also typically controlled within a specified range. Therefore, although there is some variation in these three factors, the major determinant of the channel's response and bandwidth is the configuration and number of devices. This is illustrated in FIG. 8. FIG. 8 illustrates the channel response from the Master to the last Slave device on the channel (i.e. the forward transmission to device D.sub.N) for three system configurations, 16-8-8, 8-4-0, and 4-0-0. The solid line for each configuration plots the typical response while the shading around each line indicates the range of likely channel responses for that configuration considering manufacturing variations in device pitch, input capacitance, and loss (both R.sub.I and channel losses). FIG. 8 suggests that the channel characteristics are largely determined by the system configuration, such that transmission of data through Bus System (to the last device) depends strongly on the configuration used (i.e. number and type of modules used). Thus, it may be possible to improve the performance of the Bus System by adjusting transmitter or receiver parameters in response to the particular system configuration that is being used in order to compensate for the configuration-dependent transmission characteristics.
FIG. 9 illustrates the channel response between the Master and the first, middle, and last Slaves in an N-device Bus System. The solid lines in FIG. 9 plot the typical response for the first, middle, and Nth device while the shading around each line indicates the range of likely channel responses for that device position considering manufacturing variations in device pitch, input capacitance , and loss. FIG. 9 suggests that for a given channel configuration, the channel characteristics between the Master and any individual slave is largely determined by the position of the slave device within the Bus System configuration. Thus, the Bus System performance may be improved between the Master and each individual Slave by adjusting certain transmitter or receiver parameters according to which Slave is being addressed, thus compensating for the position-dependent channel characteristics.
FIG. 10 illustrates the channel response between the Master and the Slave on each of three modules of a three-module Bus System. The solid lines of FIG. 10 plot the typical response of the middle device in each of the three modules while the shading around the line for Module B indicates the range of channel responses for Slaves on that module. This range of channel responses takes into account manufacturing variations in device pitch, input capacitance, and loss as well as the range of physical positions within the module. The range of channel responses on Module A may overlap the range of channel responses for Module B, and similarly the range of channel responses on Module C may overlaps that of Module B. FIG. 10 suggests that for a given channel configuration, the channel characteristics between the Master and any individual Slave is largely determined by the Module on which the Slave is located. Thus, it may be possible to improve the performance of the Bus System by adjusting certain transmitter or receiver parameters according to which Module is being addressed to compensate for the Module position-dependent channel characteristics.
FIGS. 8-10 demonstrate that although Bus Systems with the same configuration have individual differences, electrical characteristics can generally be associated with each configuration, Module, or Slave position. For example, a 4-4-0 Bus System generally has less attenuation than a 4-8-0 Bus System, therefore, signaling between the Master and any Slave depends on the individual device characteristics, its position in the Bus System, and the configuration of the Bus System.
FIG. 11 illustrates the effect of position-dependent channel characteristics on binary signaling between the master device and various slave devices in a system. FIG. 11A shows what a . . . 101010 . . . binary data pattern might look like when it is transmitted at the Master. The signal at the Master has a fairly large amplitude given by the equation V.sub.swing,M =(V.sub.OH,M -V.sub.OL,M)=(V.sub.Term -V.sub.OL,M)=(V.sub.L +V.sub.H).sub.,M and has sharp rise and fall times indicated in FIG. 11A as t.sub.r and t.sub.f, respectively. Additionally, the transmitted signal is asymmetric relative to the reference voltage, .sub.Vref. The amount of asymmetry is measured by the equation: ##EQU3##
As the signal propagates down the channel, its shape is altered by the channel's response. For a low pass channel as shown in FIGS. 4-10, both the signal's amplitude and edge rate will decrease as it propagates down the channel. For example, FIG. 11B illustrates what the signal of FIG. 11A might look like by the time it reaches the middle Slave, and FIG. 11C shows what it may look like by the time it reaches the end of the channel. The decreased amplitude lowers the Bus System's voltage margin whereas the slower edge rates decreases the timing margin. FIGS. 11A-11C also illustrate how voltage asymmetry varies based upon the position of the receiving device with respect to the master.
Referring now to FIG. 12A, configuration dependent channel characteristics may give rise to an undesired timing skew between clock and data signals as they propagate from the transmitting device (which may be the Master or a Slave) to the receiving device (which may be a Slave or the Master). Ideally, data signals should be detected by the receiving device at a time t1 during the data eye. As used herein, "data eye" refers to the period, denoted "tbit," during which valid data is on the bus between data transition periods. Time t.sub.1 corresponds to the center of the data eye and it provides maximum timing margin, 1/2+L tbit, for data detection between data transition periods. When the clock transition occurs in the center of the data eye, "timing center" is said to exist. FIG. 12A illustrates this ideal relationship between the data signal and the receiving device's receive clock signal. A data signal transmitted so that it aligns ideally with respect to a receiving device's receive clock signal may arrive at the receiving device early or late with respect to the receiving device's receive clock signal. In some embodiments, the best data receive time may be at another point within the data eye, other than the center, due to known or predicted characteristics of the data channel.
It is well known that channel characteristics introduce undesired timing skew between the receive clock signal and data signals at the time of detection that varies as a function of the position of the receiving device with respect to the transmitting device and the direction of signal transmission. For example, channel characteristics may cause the Master to read data from Slaves too early in the data eye and may cause the Master to write data to the Slaves too late in the data eye. How early or late the Master reads or writes depends upon the system configuration and the location of each Slave relative the master. FIG. 12B is a timing diagram illustrating the master's receive clock signal transition occurring early in the data eye by an error period of .delta.. FIG. 12C is a timing diagram illustrating the Master's transmit clock transition occurring late in the data eye by an error period of .delta..
Corruption of data transmitted via the Bus results not only from static characteristics, but also from data dependent phenomenon such as residual and cross-coupled signals. Residual signals on the Bus result from past transmissions on the same channel and tend to cause voltage margins on the channel to vary from one sampling interval to the next. Cross-coupled signals result from inductive coupling of signals on neighboring channels, rather than from past signals on the same channel. Cross-coupled signals also tend to cause voltage margins on the channel to vary from one sampling interval to the next. Herein voltage margin variations caused by residual signals are referred to as temporal variations while margin variations caused by cross-coupled signals are referred to as cross-coupling variations.
FIG. 25 illustrates a bit-stream of 0, 1, 1, 0, transmitted on the Bus, which exhibits the voltage margin variation that can result from residual signals. The voltage on the channel rises to V.sub.HI during transmission of the first logical 0. As, the voltage on the channel does not reach V.sub.LO during transmission of the first logical 1, instead reaching a local minimum 200 mV above V.sub.LO. By contrast, the voltage on the channel drops 100 mV below V.sub.LO during transmission of the final logical 1. Finally, the voltage on the channel reaches a local maximum 200 mV below V.sub.HI during transmission of the final logical 0. FIG. 25 thus illustrates how an output signal on a channel is affected by prior transmissions on the same channel. In general, a logical 1 that follows a logical 0 is less likely to reach V.sub.LO than a logical 1 that follows transmission of another logical 1. Similarly, a logical 0 that follows a logical 1 is less likely to reach V.sub.HI than a logical 0 that follows transmission of another logical 0. Both of these effects result in reduced voltage margins at the receiver, making the Bus System more susceptible to bit errors caused by noise and other margin-reducing effects.
To offset some of the channel's corrupting effects on data signals, prior art systems have used a combination of adjustable parameters; e.g. these parameters include: edge or slew rate control and current or swing control. These parameters are typically set to improve communication with the last Slave on the channel, and the parameters are then held constant no matter which Slave is accessed. This technique often does improve the performance of the Bus System. For example, adjusting the current control such that the last Slave on the channel received a balanced, full swing signal certainly improves communication between the Master and the last Slave. Communication between these two devices might otherwise be unreliable. However, adjusting the swing such that the last Slave is improved can corrupt communication between the Master and the first few Slaves on the channel. For example, reflections of this large, asymmetric signal at channel discontinuities near the first few Slaves can severely degrade the voltage margin of the first few Slaves, particularly the V.sub.H voltage margin. Secondly, the large asymmetry at the first few Slaves causes duty cycle error since .sub.VREF is not at the center of the data waveform. This degrades the timing margin at the first few devices. Therefore, a need exists for a Bus System that adjusts its transmitter, channel, and/or receiver parameters to improve communication between the Master and any Slave on the channel.